According to the study by the inventors of the present invention, the following technologies for improving the reliability of the DRAM are known.
For example, Japanese Patent Application Laid-Open Publication No. 2003-77294 (Patent Document 1) describes a memory circuit as shown in FIG. 21. The memory circuit shown in FIG. 21 has a structure in which the data from memory cells of SRAM or DRAM is checked and corrected in the error correction code circuits (ECC circuit). If the structure as described above is used, even when error occurs in the data bit of 4 bits, the error can be corrected by using the check bit of 3 bits.
Further, a plurality of ECC circuits are provided to a memory array and the data from the bit lines not adjacent to each other are connected to each ECC circuit in FIG. 21, and the error correction is performed in this structure. Therefore, even when the so-called multi-bit soft error occurs in a plurality of consecutive bit lines, the error correction can be performed. Also, redundant memory cells are provided in order to replace the stuck failure, and the data from the normal memory cell and the data from the redundant memory cell can be replaced in the course of connection from the sense amplifier circuit to the ECC circuits.